请帮分析下这个Makefile!!!!
各位好,刚开始学习makefile 看到有如下的makefile ,最后几行没有看明白,请各位帮忙看下,谢谢了


include ../Makefile.param
include ../../../makefile.param

CFLAGS += -Wall -g $(INC_PATH)


UTIL_SRC := /home/guosmb/Hi3515_SDK_V1.0.2.0.c1/sno_ipncv2/interface/src/msg_util.c
UTIL_SRC += /home/guosmb/Hi3515_SDK_V1.0.2.0.c1/sno_ipncv2/interface/src/sem_util.c
UTIL_OBJ := $(UTIL_SRC:%.c=%.o)

# common source
COMM_SRC := $(MPP_PATH)/sample/common/sample_common.c
COMM_OBJ := $(COMM_SRC:%.c=%.o)

# target source
SRC := $(wildcard *.c) 
OBJ := $(SRC:%.c=%.o)

TARGET := $(OBJ:%.o=%)
.PHONY : clean all

all: $(TARGET)

$(TARGET):%:%.o $(COMM_OBJ) $(UTIL_OBJ)
$(CC) $(CFLAGS) -lpthread -lm -o $@ $^ $(LIBS)
echo ===cp ===
cp sample_venc /home/guosmb/Hi3515_SDK_V1.0.2.0.c1/rootfs-FULL_REL/home/network/
clean:
@rm -f $(TARGET)
@rm -f $(OBJ)
@rm -f $(COMM_OBJ)

/*-----------------------------------------------*/
如上所示,粗体的不是很明白,特别是"TARGET := $(OBJ:%.o=%)" 更不明白,还请多多帮忙,谢谢!


------解决方案--------------------
TARGET := $(OBJ:%.o=%) // 生成目标 比如 $OBJ是a.o b.o则$TARGET就是a b
.PHONY : clean all // 伪目标

all: $(TARGET) // make 要生成 $TARGET

$(TARGET):%:%.o $(COMM_OBJ) $(UTIL_OBJ) // 描述依赖关系与目标 比如 a就是 a:a.o $(COMM_OBJ) $(UTIL_OBJ) 
$(CC) $(CFLAGS) -lpthread -lm -o $@ $^ $(LIBS) // 生成目标执行的命令